Automates transistor-level CMOS OTA design using the gm/ID methodology. On your PDK, on your machine, with results you can verify step by step.
AmpForge consists of two integrated tools that take you from a foundry SPICE model to a verified, ready-to-simulate SPICE netlist — without leaving the GUI.
Enter your OTA topology, supply voltage, and performance specifications. Auto Mode explores the full design space and simultaneously returns three solutions — Low Power, Balanced, and High Slew Rate — each with a SPICE netlist and CSV design report.
Manual Mode lets you set channel length and overdrive voltage directly for fine-tuning, corner optimisation, or single-transistor sizing.
The MOS Characterizer generates the .mdat characteristic database that the Design Synthesizer uses for sizing. It runs entirely on your machine using NGSPICE — the foundry SPICE model file never leaves your system.
Pre-built .mdat files are included for SCL 180nm, IHP 130nm, and GF 180nm, so you can start designing immediately without running extraction.
Pre-built MOS characteristic databases are included. Point AmpForge at the .mdat directory and run your first OTA design in minutes.
Differential Amplifier, Symmetrical, Folded Cascode, Recycling Folded Cascode, Two Stage Miller variants, Class AB — and more.
AmpForge results have been verified against SPICE simulation. The tool ships with worked examples showing achieved vs. simulated specs side by side.
No internet connection required for day-to-day use. Internet is needed once — to send your Machine ID and receive your licence file.
AmpForge was designed for the engineers, researchers, and institutions driving India's analog IC capability.
C-DAC, IITs, NITs, and research institutions working under C2S, ChipIN, and MeitY programmes. AmpForge is node-locked and can be deployed on a shared lab server — one licence, multiple concurrent users.
Engineering teams who need to shorten the OTA sizing iteration loop. Manual sizing using hand calculations and iterative SPICE runs takes weeks. AmpForge compresses that to minutes, with three verified starting points.
Fabless startups working on SCL 180nm or open-source PDKs (IHP 130nm, GF 180nm) who need production-ready SPICE netlists without a full EDA stack.
Course instructors and graduate students who want to demonstrate or learn the gm/ID methodology with real outputs — not simulated examples.
Request a trial or full licence. We respond within 48 hours with your .lic file.